= Reset charge-injection pedestal
{title2=$|\Delta v|=|Q_{\rm inj}|/C$}
A \b[reset charge-injection pedestal] is a step in the initial integrator output caused by charge transferred when the reset switch changes state. It can remain after an arbitrarily long preceding discharge. The <integrator reset> article distinguishes it from a decaying residual; the physical switched-integrator datasheet separately specifies charge-transfer errors.<ACF2101 Low Noise, Dual Switched Integrator datasheet>[p3, Charge Transfer Errors]{ref}
For an original example, let the net opening charge have magnitude $2\,\mathrm{pC}$ on an integration capacitance of $1\,\mathrm{nF}$. The output step has magnitude $2\,\mathrm{mV}$. If interpreted as photodiode signal charge with constant responsivity $0.50\,\mathrm{A/W}$, it would imitate $Q/R=4\,\mathrm{pJ}$ of incident energy under the linear model. A positive step interpreted as signal would bias a true $20\,\mathrm{pJ}$ measurement by $20\%$. The actual polarity depends on the circuit.
Repeated zero-input acquisitions at the same post-opening delay estimate the mean pedestal. Subtracting that mean does not remove <reset pedestal variance>. For a fixed capacitance, an opening-charge standard deviation of $0.10\,\mathrm{pC}$ gives an output standard deviation of $0.10\,\mathrm{mV}$ in the same stipulated model.
Varying the preceding reset duration helps distinguish residual discharge from a step created by opening. Gain, capacitance, signal level and readout delay must remain comparable. Adding capacitance can reduce the step per unit charge but also changes the signal conversion and the full circuit's settling behavior.
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