Ripple counter
= Ripple counter
A cascade in which an output transition of one <flip-flop> clocks the next. With positive-edge-triggered toggle stages and uncomplemented $Q$ connections, it decrements modulo $2^n$: a zero <bit> rises to one and propagates a borrow, while a one <bit> falls to zero and stops propagation. Ripple propagation takes time, so intermediate transient states are not the settled counter state.