= SR250 Gated Integrator by Stanford Research Systems
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https://www.thinksrs.com/downloads/pdfs/catalog/SR250c.pdf
Manufacturer catalogue. PDFp1 Overview: adjustable gate delay, integration and normalization by gate width. PDFp2 Gate Timing and Polarity Control and Active Baseline Subtraction: oscilloscope gate monitor, alternate signal/baseline triggers and polarity reversal.
PDF p2, Gate Timing and Additional Outputs; p3, Delay/Jitter. The descriptive text combines20ps and0.01% of full-scale delay with a plus sign, whereas the specification table says “whichever is larger”. These passages therefore do not specify an identical numerical jitter model.
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