= Static-one logic hazard
A <logic hazard> in which an output intended to remain one briefly falls to zero. In a <sum of products>, cover every adjacent pair of one-cells in a <Karnaugh map> with a common product <implicant>. That term omits the changing input and remains one throughout the transition, holding the OR output high regardless of the other path delays. This argument assumes one input changes at a time and the circuit starts settled.
For a concrete circuit, let $x=\bar a\bar c$, $y=bc$, $z=\bar cd$, $w=y+z$ and $q=x+w$. Give every gate, including each inverter, <propagation delay> 10 ns. Starting from $a=b=c=d=1$, lower $c$ at time zero. Signal $y$ falls at 10 ns, while $z$ rises only at 20 ns. Their gap passes through the two OR gates, making $q$ fall during 30–40 ns even though its steady-state value remains one.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2018/digital-systems-static-hazard-waveforms.png]
{title=A <static-one logic hazard> from unequal inversion and product paths}
Adding the two <consensus theorem> products $\bar ab$ and $bd$ preserves the <Boolean function> and holds the output high across every potentially hazardous single-input transition. The resulting five-term expression factors as $q=bc+(\bar a+d)(b+\bar c)$. When a change of $c$ could leave the output steadily one, $b=1$ and $\bar a+d=1$ keep the second product steadily one. In the zero-to-zero case with changing $c$, $b=0$ and $\bar a+d=0$ keep both output products zero. Changes of $a,b,d$ use only one polarity each and therefore have no opposite-polarity race. This factored implementation uses three OR gates, two AND gates and two NOT gates, with a 40 ns maximum input-to-output path at the stated delays.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2018/digital-systems-hazard-free-factorization.png]
{title=A shared-factor implementation of the <consensus theorem> correction}
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