= Synchronous 110 detector
{title2=$z_k=a_{k-2}a_{k-1}(1-a_k)$}
A <synchronous sequential circuit> emitting a one-cycle pulse at the first low sample after at least two consecutive high samples. Three <D flip-flops> can implement $q_1^+=a$, $q_2^+=q_1\land a$, and $z^+=q_2\land\neg a$, with all updates using the old state. Initializing all state bits to zero excludes a false startup history. The stored output changes only at clock edges. After a detecting low sample, $q_2$ becomes zero, so the next output is zero regardless of the next input. A longer high run still ends with the same three-sample pattern.
Back to article page
