TLB hit (source code)
= TLB hit
{c}
A lookup that finds a valid cached <address translation> for the relevant <address space>. The access can still cause a <page fault> if the cached permissions forbid it.
For the 64-<byte> toy model in <address translation>, a cached process A page-4 mapping covers reads at both `0x12D` and `0x12E`, yielding <physical addresses> `0x36D` and `0x36E`. The <TLB hit> reuses the mapping; it does not guarantee that either requested <byte> is in a data <memory cache>.
Back to article page