= Translation lookaside buffer
{title2=TLB}
{wiki}
A <translation lookaside buffer> is a small hardware <memory cache> of <virtual address> to <physical address> mappings and their access attributes. A <TLB hit> finds a usable cached mapping for the current <address space>; access permissions still apply. A <TLB miss> means that mapping is absent from the <translation lookaside buffer>. It says nothing by itself about whether the <memory page> is resident. Evicting a <translation lookaside buffer> entry removes a cached translation, not the <memory page>'s contents. https://docs.amd.com/api/khub/documents/sD1_QL~h4Afq2_tvzxqqSQ/content[AMD64 Architecture Programmer's Manual, volume 2, revision 3.44, section 5.5: Translation-Lookaside Buffer]{ref}
For the 256-<byte> example, a cached virtual page `0x12` to physical frame `0x07` mapping covers every offset from `0x00` to `0xff`. Reads at <virtual addresses> `0x1234` and `0x1235` can reuse it to reach <physical addresses> `0x0734` and `0x0735`. If the <translation lookaside buffer> is initially empty, the first read instead requires a <page table walk>; with a resident, readable mapping, it completes without a <page fault>. A write can fault even on a <TLB hit> because cached permissions deny it.
\Image[/tlb-miss-versus-page-fault.png]
{title=A TLB miss can refill a resident translation without a page fault; permission failures can fault on a TLB hit}
The diagrams show an ordinary <x86> model with hardware <page table walks>. Some architectures use an <operating system> handler to refill the <translation lookaside buffer> after a <TLB miss>; that refill event alone is not a nonresident <page fault>. <Temporal locality> helps a small <translation lookaside buffer> serve repeated accesses, and one entry can cover many <bytes>. <Operating Systems: Three Easy Pieces by Remzi H. Arpaci-Dusseau and others/Paging: Faster Translations (TLBs)>[Operating Systems: Three Easy Pieces by Remzi H. Arpaci-Dusseau and others; Arpaci-Dusseau and Arpaci-Dusseau, OSTEP chapter 19: Paging, Faster Translations, sections 19.1 and 19.3]{ref}
A <context switch> does not universally flush the whole <translation lookaside buffer>. An <address space identifier> can distinguish translations with the same virtual page number in different <address spaces>; Intel's PCIDs support retaining translations across appropriate switches. The <operating system> must still invalidate stale translations when mappings or permissions change, following the architecture's rules, including coordination with other processors that could use them. https://cdrdv2-public.intel.com/825743/325462-sdm-vol-1-2abcd-3abcd-4.pdf[Intel SDM, volume 3A, sections 4.10.1 and 4.10.4–4.10.5: PCIDs and translation invalidation]{ref}
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