= Understanding POWER Multiprocessors (2011)
{c}
{title2=PLDI 2011}
Primary research article: https://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf
Section 2.1 introduces store buffering and message passing. Section 2.2 explains barriers and dependencies, including why a genuine <address dependency> can order reads while a bare <control dependency> does not. This source corroborates the general <memory model> discussion, not the availability of examination answers.
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