= Formal equivalence checking
{wiki=Formal_equivalence_checking}
Formal equivalence checking is a method used in the verification of digital circuits and systems to determine whether two representations of a design are equivalent in terms of their functionality. This technique is commonly employed in the context of hardware design, particularly in the realm of integrated circuit (IC) design, and it can be used to compare high-level specifications, synthesized netlists, or gate-level implementations.
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