 Solution

The opcode occupies bits $31:26$, the arithmetic logic unit operation is wired directly to $15:10$, and an immediate operand uses all of $9:0$. A three-register instruction needs fifteen register-selection bits, whereas an immediate instruction must retain independent source and destination selectors outside $9:0$.

Thus put $r_s$ and $r_d$ in the ten bits $25:16$, and place $r_t$ in five of $9:0$, where it can overlap the unused immediate operand of a register instruction. One valid instruction encoding isBits $4:0$ are unused for a three-register instruction. In an immediate instruction, $r_t$ has no effect because its read value is deselected by the ToAlu multiplexer. In a store, $r_s$ selects the address and $r_t$ selects the data; $r_d$ must be zero to suppress the incidental register write. These observations follow the original datapath, particularly its direct $va{l}_s$ memory-address connection and the connection from the ToAlu output to memory write data.^[ref]