Solution

ID: past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2016/digital-systems-linear-algebra-introduction-to-formal-proof-resit/3/c/solution

Conditioning on a cache hit or cache miss, the expected latency is
This is a straight line from to ; at hit rate , the mean is 23 ms. The 45 ms is already the complete miss-service time in the question, so another cache-lookup millisecond is not added to it.
Figure 1. . Original plot of milliseconds, including the endpoint and midpoint values. Details.

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