 PCI Express lane

A PCI Express lane contains one transmit differential signal pair and one receive differential signal pair. Each pair carries a serial signal, and the separate transmit and receive paths permit traffic in both directions. Multiple lanes can form a wider PCI Express link.^[ref]

For example, an x4 link groups four lanes. At the same per-lane signaling rate it has four times the raw one-direction capacity of an x1 link, before encoding and protocol overhead. A PCI Express lane is not one individual conductor, and a connector's physical size does not by itself establish the negotiated link width. Payload throughput depends on the actual width, rate, encoding and transaction traffic.