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cirosantilli/verilog/

by Ciro Santilli (@cirosantilli, 37)
  • interactive/
  • .gitignore
  • clean
  • common.hpp
  • counter_syn.v
  • counter_tb.v
  • counter.cpp
  • counter.params
  • counter.v
  • display_tb.v
  • error_tb.v
  • Makefile
  • monitor_tb.v
  • negator_tb.v
  • negator.cpp
  • negator.params
  • negator.v
  • ram_dual_tb.v
  • ram_dual.v
  • ram_tb.v
  • ram.v
  • run
  • run-many
  • run-verilator-one
  • subleq.cpp
  • subleq.params
  • subleq.v
  • two_modules_tb.v
  • two_modules.v
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