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The computer bus path identifying the destination or location of a bus transaction. An initiator supplies an address; decoding selects the intended target. Address width describes the available address encodings, whereas data bus width describes how many bits can be carried at once.^[ref]

A group of related payload transfers, often to consecutive addresses, arranged under one transfer sequence. A bus burst can amortize setup and bus arbitration overhead; a longer period of exclusive bus ownership can also make another initiator wait longer. The exact overhead and permitted handover boundaries depend on the protocol.^[ref]

One requested operation and its completion, potentially including several payload transfers. A bus transaction identifies a target, specifies an operation and exchanges data or status. A CPU or DMA engine can initiate one; a target responds. The terms “master” and “slave” in older hardware documents refer to these initiator and target roles.^[ref]

An extension while a bus transaction awaits readiness. A bus wait state spends time without completing the next payload transfer. In a blocking design it also postpones another initiator's access; completion and bus ownership changes must follow the protocol.^[ref]