The processor executing a program's instructions. In polled input-output the CPU explicitly checks status; in interrupt-driven input-output it enters an interrupt handler; in DMA it delegates payload movement while retaining setup and completion work.
Executing ready instructions before older instructions whose operands or resources are unavailable, while preserving the specified architectural behavior. Reservation stations, register renaming and a reorder buffer support different parts of this organization.
An age-ordered structure holding issued instructions' results and completion or exception status until instruction retirement. It permits execution to complete out of order while commitment follows program order.
Committing a completed instruction's architectural effects in program order. An instruction with no register result still needs completion status before instruction retirement can pass it.
A shared path carrying tagged results or completion information to waiting reservation stations, the register file or a reorder buffer. A tag identifies the particular producer, not merely the destination's logical name.
Mapping logical processor registers to versions identified by producer tags or physical registers. A conditional destination must still deliver the old logical value when its predicate is false.
A hardware value-storage location distinguished from an architectural processor register name. Several live versions of one logical register can occupy different physical registers.
Storage for an issued instruction and its operands or producer tags until execution can proceed. In a scheme using station identifiers as persistent result tags, the identifier cannot be reused before the old result has completed writeback.
A processor with several CPU cores that can execute instruction streams concurrently. Shared computer memory requires attention to cache coherence and the architecture's memory model.
An execution core within a processor. Each CPU core can have a private memory cache and store buffer while participating in a coherent memory system.
Executing work before a condition validating it is resolved. Correctness requires suppressing or recovering its architectural effects if the condition fails. A reorder buffer supports controlled instruction retirement of such work.
Predicting a branch's continuation before its outcome is known, allowing instruction fetch and potentially execution to proceed. An incorrect prediction requires recovery of younger speculative work.
Instruction pipelining divides execution into stages with stored intermediate state, allowing different instructions to occupy different stages simultaneously. The processor clock period is constrained by stage timing; moving a barrel shifter and arithmetic logic unit into the same stage can lengthen that stage's combinational critical path.
An execution-timing conflict arising from the ordering of accesses to a value. A read-after-write hazard occurs when a consumer would read before its required producer's value becomes available.
A younger instruction needs a value produced by an older instruction before the ordinary writeback/read path would deliver it. Register forwarding or a pipeline stall can enforce the true dependence.
Sending an already produced result directly to a consumer without waiting for its write to the register file. The bypass must choose the youngest older writer whose value is ready.
An interval in which some stage cannot advance its instruction. A data hazard, occupied resource or unresolved cache miss can cause a pipeline stall.
Storage between stages of an instruction pipelining implementation, holding intermediate operands, results and control information across a clock boundary.
An instruction pipelining organization in which instructions advance through execution in program order. Different instructions can occupy different stages simultaneously, and register forwarding can remove some data hazards.
A datapath comprises the processor registers, functional units and connections through which instruction operands and results move. Control signals select operand sources, operations, memory access and processor register writeback. Connecting a barrel shifter before an arithmetic logic unit permits shift-and-add operations in one pass, but puts their delays in series.
A component executing a class of operations, such as addition or multiplication. Operand availability, unit occupancy and result-broadcast capacity can independently constrain its scheduling.
An arithmetic logic unit is a combinational logic component that performs selected arithmetic or bitwise operations on its input machine words. Its result and status outputs, such as a carry flag, depend on the operation control. A datapath may require a pass-through operation as well as addition, particularly when a barrel shifter feeds an operand.
Busy waiting repeatedly tests a condition while keeping the processor occupied. A delay based only on instruction counts also depends on instruction timing and time spent handling interrupts. Polling a hardware timer avoids that calibration dependence but still occupies the processor.
A small storage location within a CPU used by its instructions. Some hold data; others describe control state, such as the program counter or stack pointer. Saving and restoring processor registers lets different software threads reuse the same CPU while retaining separate execution contexts.
State bits recording properties of an instruction's result for later conditional operations. A branch must use the flags established by the intended preceding instruction: an intervening flag-setting operation can change its meaning.
A processor condition flag set when the relevant result is zero. A loop that decrements its remaining count and immediately branches on nonzero uses this flag as its termination test. A preceding logical shift's zero result is a different condition.
A processor status bit recording arithmetic carry. For unsigned addition of -bit inputs, , where is the stored result. In the ARM architecture family, subtraction instead uses , so a set arithmetic carry means no borrow. This convention must be checked for the target instruction set; it is not a signed-overflow test.
With the ARM architecture family's no-borrow convention, subtract with carry forms . The same adder used for addition can form . If its output is , rearranging proves . Thus complementing the second operand implements both the result and the correctly chained borrow information.[ref]
For -bit operands, an add with carry operation forms , retains its residue modulo , and outputs its arithmetic carry. Adding low limbs first and feeding each arithmetic carry into the next limb implements multiword unsigned addition. With , the identities and combine into .[ref]
Thumb 16-bit instruction set quick reference by Arm. Page 1, Add with carry
A collection of indexed processor registers. Selecting one of registers requires at least bits in a register index field.
A destination code whose writes have no architectural effect. Replacing a disabled write by a write to such a destination can remove a global register-file enable input: every actual register enable becomes its address-decode line, and the suppression code activates none. The instruction control must still select that code whenever a write should be suppressed. This transformation preserves the register-state update, rather than making the control decision unnecessary.
Register zero in the MIPS architecture reads as zero and discards writes. An implementation can omit its data storage, hardwire its read output to zero and suppress its write selection. This property permits using zero as a write-suppression destination without changing the visible register values.
Moving a live value from a processor register to memory so the register can be reused, then loading it again when needed.
A processor register identifying the current position in a stack, commonly a call stack; the exact convention depends on the architecture. Restoring a stack pointer selects the saved stack position, rather than copying the whole call stack.
