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Intel QuickPath Interconnect is a packet-based point-to-point interconnect designed for communication among CPUs and other system components. It includes a cache coherence protocol, allowing distributed memory caches and memory controllers to participate in a coherent memory system. Its layered design separates electrical transmission, reliable link transfer, routing and higher-level transactions.^[ref]

For example, a CPU requesting a cache line may obtain the current data from another CPU's memory cache, coordinated by the cache coherence protocol. The Intel QuickPath Interconnect link layer uses credits representing available receiving buffers: transmission consumes credits, and freeing buffers returns them. This controls how much data the receiver must accept.^[ref]

As with PCI Express, independent links can operate concurrently while traffic sharing a link or destination can contend. The shared buses and point-to-point links distinction prevents applying a single globally shared bus model to the entire interconnect.

// Destination: computer-science.bigb