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Byte-lane immediate 2026-10-31

An instruction encoding that stores an eight-bit byte and a two-bit byte-position selector, expanding them to a 32-bit machine word as

b 2^{8 j}

for

0 \leq j \leq 3

. Four such values can construct any 32-bit constant using bitwise OR or addition modulo

2^{32}

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Past exam of the year 1 of the computer science course of the University of Oxford / 2013 / Digital systems, linear algebra, introduction to formal proof / 2 / c / Solution 2026-10-31

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Choose ToAlu=0 for the

v a l_{t}

input and ToAlu=1 for the expanded immediate operand. Choose ToReg=0 for the arithmetic logic unit result and ToReg=1 for memory read data. The diagram does not label the multiplexer polarities, so these are explicit conventions.

Let

F_{+}

and

F_{\lor}

denote the six-bit arithmetic logic unit operation codes for addition and bitwise OR. Their numerical codes are not specified by the paper. The opcode needs to distinguish register, immediate, load and store modes; add and or can share register mode, and addi and ori can share immediate mode, since

15 : 10

selects the operation directly. For example, choose

o_{R} = 000000

o_{I} = 000001

o_{L} = 000010

and

o_{S} = 000011

. With

X

denoting a field whose bits do not matter, the formats are:

Table 1.

One consistent allocation of instruction encoding fields

Instruction	$31 : 26$	$25 : 21$	$20 : 16$	$15 : 10$	$9 : 5$	$4 : 0$
`add d,s,t`	$o_{R}$	$s$	$d$	$F_{+}$	$t$	$X$
`or d,s,t`	$o_{R}$	$s$	$d$	$F_{\lor}$	$t$	$X$
`addi d,s,x`	$o_{I}$	$s$	$d$	$F_{+}$	Upper five bits of $x$	Lower five bits of $x$
`ori d,s,x`	$o_{I}$	$s$	$d$	$F_{\lor}$	Upper five bits of $x$	Lower five bits of $x$
`load d,(s)`	$o_{L}$	$s$	$d$	$X$	$X$	$X$
`store t,(s)`	$o_{S}$	$s$	$0$	$X$	$t$	$X$

The required opcode control table is:

Table 2.

Control values required by the pictured datapath

Mode and instructions	`ToAlu`	`MemWr`	`MemRd`	`ToReg`
$o_{R}$ : `add`, `or`	$0$	$0$	$X$	$0$
$o_{I}$ : `addi`, `ori`	$1$	$0$	$X$	$0$
$o_{L}$ : `load`	$X$	$0$	$1$	$1$
$o_{S}$ : `store`	$0$	$1$	$X$	$X$

Here MemRd is irrelevant whenever read data is unused, under the ordinary side-effect-free memory interpretation of the diagram. It is sensible to choose zero for those

X

entries to save activity; memory-mapped devices with read side effects would require that choice. For store, ToReg is irrelevant because

r_{d} = 0

; ToAlu is essential because its output supplies both the second arithmetic logic unit operand and memory write data. For load, the memory address is

v a l_{s}

independently of ToAlu and of

15 : 10

The resulting effects, with 32-bit addition, are

add : addi : load : R_{d} \leftarrow R_{s} + R_{t}, R_{d} \leftarrow R_{s} + E (x), R_{d} \leftarrow M [R_{s}], or : ori : store : R_{d} \leftarrow R_{s} ∣ R_{t}, R_{d} \leftarrow R_{s} ∣ E (x), M [R_{s}] \leftarrow R_{t},

(1)

where

E (x) = (x mod 256) 2^{8 ⌊ x /256 ⌋}

for the ten-bit field

x

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Past exam of the year 1 of the computer science course of the University of Oxford / 2014 / Digital systems, linear algebra, introduction to formal proof / 1 / b / Solution 2026-10-31

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Add zero extension alongside sign extension, and a multiplexer controlled by a new signal ExtSign to select between them before the existing immediate-input connection. Equivalently, make the extender itself selectable:

extended_{15 : 0} = n, extended_{31 : 16} = {n_{15} \dots n_{15}, 0 \dots 0, ExtSign = 1, ExtSign = 0.

(1)

Decode ori to ExtSign=0, RegDst=0, ALUSrc=1, RegWrite=1 and ALUFunc=OR. The arithmetic logic unit then performs bitwise OR between

y

and the zero-extended immediate operand and writes the result to

x

. Extend the arithmetic logic unit's control decoding if OR was not already available. Decode addi to ExtSign=1; the new signal is irrelevant for MIPS R-type instructions because ALUSrc=0.

Zero extension matters even when the most significant immediate bit is one: ori with 0x8000 must only affect the low half of the destination, whereas sign extension would incorrectly force every high bit to one.^[ref]

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