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Automatic power factor correction adjusts a correction device as the measured load changes, rather than leaving one fixed compensating setting connected. In a staged capacitor bank, a controller uses terminal electric potential difference and electric current information to choose which stages are connected. The controlled quantity and target must distinguish active power, signed reactive power, waveform distortion and the chosen lead/lag convention.

For an original single-phase sinusoidal model, available stages each supply $q_s$ of capacitive reactive power at the operating electric potential difference. With $k$ connected stages,At fixed $P>0$, maximizing the magnitude of the power factor chooses the available integer $k$ minimizing $|Q_L-k{q}_s|$. Away from the end limits, nearest-stage rounding leaves $|Q_{\mathrm{net}}|\le q_s/2$. This capacitor-stage quantization error can be positive or negative. A policy forbidding leading operation instead restricts $k{q}_s\le Q_L$, so it can choose a different setting.

Suppose $P=1000\mathrm{W}$, $Q_L=640\mathrm{var}$ and $q_s=250\mathrm{var}$. Three stages leave $-110\mathrm{var}$ and factor about $0.9940$ leading; two stages leave $+140\mathrm{var}$ and factor about $0.9903$ lagging. Both outcomes are consistent with their respective objectives. If the load changes to $P=200\mathrm{W}$, $Q_L=100\mathrm{var}$, leaving all three stages connected produces $-650\mathrm{var}$; zero stages is closer to cancellation than one. A stored stage decision must therefore be updated when the load changes.

Actual feedback must measure the corrected network. The Eaton paper places the current transformer so it senses the relevant load and capacitor contribution, and explains how a wrong phase, polarity or location produces misleading feedback.^[ref] Measuring only the correction branch would not establish the combined source power factor.

A proposed controller test varies a known resistive-inductive load through several operating points, recording stage state, signed reactive power, RMS electric current and synchronized terminal waveforms. Check both increasing and decreasing demand, including small excursions around a stage threshold. A dead band and timing rules can prevent repeated switching in response to small fluctuations; they must be specified along with the target. Stage size, switching transients and the load's harmonic components require additional checks beyond the ideal rounding model.

Capacitor-stage quantization error is the residual reactive power caused by choosing among discrete settings of a capacitor bank instead of a continuously adjustable correction. In a fixed sinusoidal operating model, let the load absorb $Q_L$ and let the target residual be $Q_t$. The desired capacitive correction is $q_{\ast }=Q_L-Q_t$. Selecting available correction $q$ leavesThe error concerns the selected setting, separately from sensing error, changing load and component tolerance.

For equal stages of magnitude $q_s$ and an available range covering the desired correction, nearest-stage selection chooses an integer $k$ nearest $q_{\ast }/q_s$. HenceAt a half-stage tie either neighbor attains the bound. A policy forbidding a negative residual relative to zero instead rounds downward and gives $0\le Q_L-k{q}_s<q_s$, away from the bank's capacity limits. The two policies solve different constrained problems.

For an original zero-target example, let $Q_L=640\mathrm{var}$ and $q_s=250\mathrm{var}$. Three stages give $r=-110\mathrm{var}$; two give $r=+140\mathrm{var}$. With active power $P=1000\mathrm{W}$, nearest-stage selection guaranteesprovided the zero-reactive target is within range and the sinusoidal fixed-load assumptions hold. At only $P=200\mathrm{W}$, the same worst-case bound falls to about $0.8480$. A stage size suitable at high demand need not give the same numerical power factor at low demand.

Unequal stages require the actual attainable set. Stages of 100 and 400 vars permit $\{0,100,400,500\}$ vars. At a desired 250 vars, the nearest setting leaves 150 vars error, despite the smallest stage being only 100 vars. The relevant bound is half the largest gap between neighboring attainable settings in the tested range, not half the smallest component. Outside the bank's range, clipping to an endpoint can leave a larger error.

At fixed frequency, a fixed capacitance gives $q_s=\omega C_s{V}^2$, so stage magnitudes also change with RMS electric potential difference. Eaton's paper describes discrete stage sizes, combinations and automatic control; the error bounds above are original consequences of that ideal setting model.^[ref] A proposed test records the actual stage states and terminal quantities while slowly varying a known load across thresholds. Compare the observed residual with the attainable-setting prediction before assigning every deviation to quantization.