Bus arbitration 2026-10-13
Selecting among initiators requesting a shared resource. An arbiter grants permission before an initiator starts its bus transaction. Fixed priority can indefinitely postpone a lower-priority requester under continuing higher-priority demand. Rotating priority can provide starvation freedom when every owner releases the resource after bounded work. Neither policy alone determines bus throughput: waiting, setup and target readiness also matter.[ref]
Lecture 21: Buses and I and O. CS152 lecture 21, slides 35–36: reservation, priority and fairness
Bus cycle 2026-10-13
One clock period in a synchronous computer bus. A bus transaction can occupy several bus cycles. An asynchronous computer bus instead coordinates progress through acknowledgments, so a clock-based count requires an additional timing model.[ref]
Lecture 21: Buses and I and O. CS152 lecture 21, slides 32–33: synchronous and asynchronous sequencing
Control bus 2026-10-13
The computer bus paths specifying operations and coordinating progress, including requests and acknowledgments. Some control travels from initiator to target and some returns. In the diagram, bus arbitration requests and grants are shown separately from transfer control to distinguish choosing an initiator from executing its bus transaction.[ref]
Lecture 21: Buses and I and O. CS152 lecture 21, slides 22 and 33–36: control signals, sequencing, request and grant
Data bus 2026-10-13
The computer bus path carrying payload. A write sends data from the initiator to the target; a read returns data from the target. Owning the request path does not mean driving the data bus in both directions.[ref]
Lecture 21: Buses and I and O. CS152 lecture 21, slide 24: initiator commands, data in either direction
Shared computer bus 2026-10-13