Shared computer bus

A computer bus whose communication resources serve multiple attached components. A common physical path reduces wiring, but competing bus transactions must share its capacity. Address bus, data bus and control bus name logical roles; they need not be three permanently separate bundles of wires. Some designs reuse lines for addresses and data in different phases.^[ref]

The computer bus path identifying the destination or location of a bus transaction. An initiator supplies an address; decoding selects the intended target. Address width describes the available address encodings, whereas data bus width describes how many bits can be carried at once.^[ref]

The computer bus path carrying payload. A write sends data from the initiator to the target; a read returns data from the target. Owning the request path does not mean driving the data bus in both directions.^[ref]

The computer bus paths specifying operations and coordinating progress, including requests and acknowledgments. Some control travels from initiator to target and some returns. In the diagram, bus arbitration requests and grants are shown separately from transfer control to distinguish choosing an initiator from executing its bus transaction.^[ref]