Use a chain of identical storage cells, each retaining the first value it sees and passing later values to the next cell. On the return journey it passes the next cell's reversed output before emitting its own retained value. This turns the chain into a distributed LIFO stack.
Here is one cell template. Its ports carry incoming values towards the tail; carry returning values towards the front. Each port carries values in , with the sentinel value outside :
An input such as abbreviates an indexed CSP external choice over the corresponding CSP events. An output is the CSP prefixing action . There is no extra controller process.
For , take copies of this same template. Introduce channels for and apply port CSP event renaming to copy , for , as follows:
At the front put and . Adjacent cells synchronize on every shared or CSP event. The two tail channels are sentinel-only: and are local tail CSP events, with no other participant required. Disable all for . Formally, use a partial relational CSP event renaming for the last copy, omitting the pairs for its with ; an unmapped transition is blocked. This explicitly prevents a fictitious tail from generating data.
Let be the resulting port-renamed cell and its visible alphabet. With consisting of the internal link CSP events, including the two tail CSP events, the answer is
Here the indexed operator is CSP alphabetized parallel composition: each CSP event is synchronized by all cells whose alphabets contain it. There are exactly storage-cell processes; port wiring and the sentinel-only tail adapt their interfaces, without adding a helper process. The local tail CSP events are hidden, as are all inter-cell communications.
To see correctness, after inputs have propagated, cell retains . The input sentinel value propagates to the tail. The last cell performs its two local tail CSP events, then returns . Inductively, if the suffix after cell returns , cell relays those values, replaces the final sentinel value by , and stops. Hence the external output is
and starts only after . Shared links provide synchronization rather than an assumption that all cells take steps simultaneously. For the degenerate known-empty input, no storage is needed: the interface is simply .
If is injective, the equation is true:
For a CSP event , the original CSP parallel composition permits exactly when both operands can perform . After CSP event renaming, the corresponding rule requires the same image in both operands. Injectivity ensures that matching images came from the same event, and that an event outside cannot acquire the image of one inside . Independent transitions remain independent, and CSP internal actions are unchanged. Matching these transition rules gives a strong bisimulation, hence equality in all three standard CSP semantic models.
For a non-injective , the equation need not hold. Let
On the left, both events require synchronization but the other operand offers the wrong event, so . On the right, both renamed operands offer , which can synchronize:
The failure is already visible in the CSP traces model. A particular non-injective CSP event renaming may still preserve a particular composition; it is the unrestricted equivalence that fails.
Use fresh event tags to tell apart an action by and an interrupting action by . Put and introduce a disjoint copy . Let fix and map each to , and put . Define a process that always accepts an event from by
and an ordinary CSP interrupt handler by
Finally let fix every original event and send back to . A simulation containing no occurrence of the new operator is
Here is the ordinary CSP interrupt, and the CSP event renaming is applied after the CSP parallel composition. It is non-injective, so part (c) explains why moving it inside would be unsafe.
Before the interrupt, 's events in synchronize with on the same events. Its events outside are unprimed and do not synchronize with . Meanwhile 's events outside are primed; they synchronize with and thereby interrupt and discard . After the first such event, the left operand is , so it imposes no further restriction on ; final CSP event renaming then yields exactly the remaining behaviour of .
For a formal strong bisimulation, relate a pre-interrupt state to
and an already-interrupted state to
The three visible cases match the rules in part (d), including both transitions when both operands offer the same event outside . A CSP internal action of never activates , while a CSP internal action of remains possible exactly until the interrupt. The controller adds no CSP internal actions. Thus transitions match in both directions and related derivatives remain related.
Consequently this simulation is stronger than merely CSP trace equivalent:
It preserves CSP stable states, their enabled-event sets and their CSP stable failures, and matches every possible infinite run of CSP internal actions. In particular, it introduces neither a premature commitment nor a new CSP divergence. A different simulation that guesses an interrupt with a hidden handshake would need a separate refusal analysis; the visible tagging construction above needs no hidden handshake.