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For a differential signal pair, the common-mode voltage is the average potential of the two conductors relative to a specified local reference:It is the component shared by both inputs. With $V_{+}=2.6$ V and $V_{-}=2.4$ V, the common component is 2.5 V and the differential component is 0.2 V. A 1 V change of the receiver's reference changes both measured conductor potentials equally and therefore changes $V_c$, while leaving $V_d$ unchanged.^[ref]

This decomposition is useful when a small sensor difference sits on a large shared offset. Even a receiver with excellent common-mode rejection ratio has a finite permitted common input range. A practical test therefore varies the average input while holding the difference fixed and checks when the output stops following its differential-gain calibration.

A differential signal pair carries information in the electric potential difference between two conductors. For conductor potentials $V_{+}$ and $V_{-}$ relative to a stated reference, define the differential and common-mode voltage components byEquivalently $V_{+}=V_c+V_d/2$ and $V_{-}=V_c-V_d/2$. A signal pair need not have zero common component; the receiver uses the difference while tolerating a specified range of common input potentials.^[ref]

Equal added disturbances cancel in the ideal subtraction: replacing both potentials by $V_{\pm }+n$ leaves $V_d$ unchanged. For example, inputs at $1.8$ and $1.2$ volts have $V_d=0.6$ volts. Adding $0.2$ volts to each changes $V_c$ but preserves the difference.

Real receivers have finite common-mode rejection ratio, and unequal coupling or mismatched impedances can convert a common disturbance into a differential one. Thus differential signalling is a system property involving the source, both paths and the receiver. An original test applies the same disturbance to both inputs and compares the output with a deliberately unbalanced path; it separates ideal cancellation from sensitivity to mismatch.

PCI Express is a packet-based input-output interconnect built from point-to-point links. A PCI Express root complex connects the host system to a hierarchy of endpoints, optionally through PCI Express switches. Each link joins two ports, so the whole hierarchy need not share one electrical path.^[ref]

A PCI Express lane contains a transmit differential signal pair and a receive differential signal pair, allowing traffic in both directions. Several PCI Express lanes can form one wider link.^[ref] For example, independent endpoint links can carry traffic concurrently, but traffic from both endpoints that converges on one upstream link competes for its available capacity. A link's payload throughput depends on its width, signaling and protocol overhead. The distinction under shared buses and point-to-point links therefore matters when interpreting the familiar term computer bus.

A PCI Express lane contains one transmit differential signal pair and one receive differential signal pair. Each pair carries a serial signal, and the separate transmit and receive paths permit traffic in both directions. Multiple lanes can form a wider PCI Express link.^[ref]

For example, an x4 link groups four lanes. At the same per-lane signaling rate it has four times the raw one-direction capacity of an x1 link, before encoding and protocol overhead. A PCI Express lane is not one individual conductor, and a connector's physical size does not by itself establish the negotiated link width. Payload throughput depends on the actual width, rate, encoding and transaction traffic.