Independent data in the same cache line cause unnecessary ownership transfers or invalidations when different CPU cores access them. A frequently written lock beside stable reader data can invalidate those data despite no logical conflict.

Ancestors (5)

  1. Cache coherence
  2. Cache (computing)
  3. Computer memory
  4. Computer science
  5. Home

Incoming links (1)

View article source

Discussion (0) New discussion

There are no discussions about this article yet.

Articles by others on the same topic (0)

There are currently no matching articles.
See all articles in the same topic Create my own version