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A combinational logic circuit adding two input bits $a,b$ to a sum bit $s=a\oplus b$ and carry bit $c=a\wedge b$. An exclusive or gate and an AND gate implement it. The identity $a+b=(a\oplus b)+2(a\wedge b)$ follows by checking the four input pairs. A half adder has no input carry, so adding three equally weighted bits needs a different circuit or multiple stages.

Generate four partial-product bits with AND gates:The binary multiplication expansion is $XY=p_{00}+2(p_{10}+p_{01})+4p_{11}$. Add the two weight-two bits with a half adder, then add its carry to $p_{11}$ with a second half adder. The complete combinational logic isThus four AND gates for the partial products and two half adders suffice. Each half adder contains one exclusive or gate and one AND gate. In the largest case $3\times 3=9$, these equations produce $1001$, including the necessary fourth output bit.