= Integrator reset settling time
{title2=$T_{\rm reset}$}
The \b[integrator reset settling time] is the time required to reach a stated error band under the reset/readout sequence. It is not merely the switch's control propagation delay. The primary switch tutorial distinguishes switching time from complete-circuit settling.<MT-088: Analog Switches and Multiplexers Basics>[pp11–13, Figures19–21]{ref}
The <integrator reset> article derives an ideal residual $V_0e^{-T/\tau}$, with $\tau=R_{\rm on}C$. A focused extension includes an opening pedestal whose magnitude is at most $p$. A conservative final-error bound is
$$
|e|\leq |V_0|e^{-T/\tau}+p.
$$
To guarantee $|e|\leq\varepsilon$ from this bound, require $\varepsilon>p$ and
$$
T\geq\tau\log\frac{|V_0|}{\varepsilon-p}
$$
when the logarithm is positive. This <reset error budget with a persistent pedestal> assigns separate parts of the tolerance to the residual and the opening event.
For stipulated $|V_0|=0.40\,\mathrm V$, $\tau=20\,\mathrm{\mu s}$, $p=2\,\mathrm{mV}$ and $\varepsilon=3\,\mathrm{mV}$, the required duration is about $119.8\,\mathrm{\mu s}$. A tolerance of $1\,\mathrm{mV}$ cannot be guaranteed by waiting longer under the same pedestal bound. Accidental cancellation of opposite-sign errors is not a worst-case guarantee.
Measure the output against a stated band at a reproducible delay after opening. Ringing, amplifier drive limits and prior overload can invalidate a single-exponential model; the device datasheet treats output-overload recovery separately.<ACF2101 Low Noise, Dual Switched Integrator datasheet>[p10, Output Overload]{ref} The resulting acquisition exclusion is part of <integrator reset dead time>.
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