Integrator reset settling time ($T_{\mathrm{reset}}$)

The integrator reset settling time is the time required to reach a stated error band under the reset/readout sequence. It is not merely the switch's control propagation delay. The primary switch tutorial distinguishes switching time from complete-circuit settling.^[ref]

The integrator reset article derives an ideal residual $V_0{e}^{-T/\tau }$, with $\tau =R_{\mathrm{on}}C$. A focused extension includes an opening pedestal whose magnitude is at most $p$. A conservative final-error bound isTo guarantee $|e|\le \epsilon$ from this bound, require $\epsilon >p$ andwhen the logarithm is positive. This reset error budget with a persistent pedestal assigns separate parts of the tolerance to the residual and the opening event.

For stipulated $|V_0|=0.40\mathrm{V}$, $\tau =20\mu \mathrm{s}$, $p=2\mathrm{mV}$ and $\epsilon =3\mathrm{mV}$, the required duration is about $119.8\mu \mathrm{s}$. A tolerance of $1\mathrm{mV}$ cannot be guaranteed by waiting longer under the same pedestal bound. Accidental cancellation of opposite-sign errors is not a worst-case guarantee.

Measure the output against a stated band at a reproducible delay after opening. Ringing, amplifier drive limits and prior overload can invalidate a single-exponential model; the device datasheet treats output-overload recovery separately.^[ref] The resulting acquisition exclusion is part of integrator reset dead time.

A reset error budget with a persistent pedestal assigns separate tolerance to a decaying pre-reset residual and an offset created when the reset switch opens. Increasing the preceding discharge time can reduce the former without reducing the latter. The integrator reset settling time article derives the basic worst-case bound and its logarithmic reset-duration requirement.

A focused extension includes leakage during a fixed post-opening readout delay $d$. Let the pre-reset residual magnitude be at most $R$, its decay time constant be $\tau$, the opening reset charge-injection pedestal magnitude be at most $p$, and subsequent electric current magnitude be at most $I_{\max }$ on fixed capacitance $C$. The triangle inequality givesThis separates a duration-controlled term from an error floor $F=p+I_{\max }d/C$. For $R>0$ and a required guarantee $|e|\le \epsilon$, finite reset time is possible from this bound only when $\epsilon >F$, and

For an original chosen circuit, take $R=0.10\mathrm{V}$, $\tau =5\mu \mathrm{s}$, $p=0.50\mathrm{mV}$, $C=100\mathrm{pF}$, $I_{\max }=1.0\mathrm{nA}$ and $d=20\mu \mathrm{s}$. Leakage consumes $0.20\mathrm{mV}$. A $1.0\mathrm{mV}$ total tolerance leaves $0.30\mathrm{mV}$ for the old residual, requiring about $29.0\mu \mathrm{s}$ of reset. A $0.60\mathrm{mV}$ tolerance requires changing the stipulated pedestal or readout conditions; reset duration alone cannot guarantee it.

These are worst-case bounds, not root-sum-square standard uncertainties. Test the discharge by varying $T$, the opening step with zero-input records, and the subsequent drift by varying $d$. Real charge transfer depends on switching sequence, and prior overload can require separate recovery.^[ref] Accidental cancellation of signed errors is not a reproducible worst-case margin.