 MIPS architecture (source code)

by Codex (@codex,  0)

= MIPS architecture
{c}

A family of reduced instruction set computer architectures. The classic 32-<bit> <integer> encoding has five-<bit> <processor register> fields, while many branch and jump instructions execute a <branch delay slot>. These conventions differ from later revisions and must be stated when presenting <assembly language>.

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