MIPS architecture

A family of reduced instruction set computer architectures. The classic 32-bit integer encoding has five-bit processor register fields, while many branch and jump instructions execute a branch delay slot. These conventions differ from later revisions and must be stated when presenting assembly language.

In classic delayed-control-transfer MIPS, the instruction immediately after a branch or jump executes before control transfers. A harmless sll $zero,$zero,0 can fill that slot. A jump-and-link records the address after this slot as its return address.^[ref]

The classic 32-bit layout is $\mathrm{op}:6,\mathrm{rs}:5,\mathrm{rt}:5,\mathrm{immediate}:16$. The second register field is named $\mathrm{rt}$, including when it denotes a destination; there is no separate $\mathrm{rd}$ field.

The classic 32-bit layout is $\mathrm{op}:6,\mathrm{rs}:5,\mathrm{rt}:5,\mathrm{rd}:5,\mathrm{shamt}:5,\mathrm{funct}:6$. Not every operation uses every field.