= Solution
Use a three-state <Moore machine> for a <rearmable one-cycle pulse generator>. Call the states `Ready`, `Pulse`, and `Wait`. Their outputs are respectively $z=0,1,0$, and initialize in `Ready`. Labels below are the sampled input pair `ab`; because simultaneous ones are unspecified, choose reset priority for `11`.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2003/computing-prelims-2003-pulse.png]
{title=Rearmable one-cycle pulse generator and reproduction of the specified timing behavior}
The complete chosen <state transition table> is
|| State
|| $z$
|| $ab=00$
|| $ab=01$
|| $ab=10$
|| $ab=11$
| `Ready`
| $0$
| `Ready`
| `Ready`
| `Pulse`
| `Ready`
| `Pulse`
| $1$
| `Wait`
| `Ready`
| `Wait`
| `Ready`
| `Wait`
| $0$
| `Wait`
| `Ready`
| `Wait`
| `Ready`
A sampled trigger `10` causes a pulse only in `Ready`. Leaving `Pulse` unconditionally on the next edge keeps its output high for exactly one <clock period>, even if `a` remains high. In `Wait`, further triggers are ignored until a sampled reset rearms the <finite-state machine>.
The crucial transition is `Pulse --01--> Ready`. If reset occurs in the cycle immediately following a trigger, this transition both ends the current pulse and rearms the circuit. The next trigger then produces a pulse after just one intervening low-output cycle. Sending every exit from `Pulse` to `Wait` would lose that reset and fail the alternate-cycle requirement. This behavior is explicitly visible in the last three pulses of the original timing diagram.<Functional programming, data structures and algorithms, procedural programming, and digital hardware examination paper by the University of Oxford (2003)>[Printed p. 8, Question 10(b)(iii), last reset and trigger alternations]{ref}
For the sixteen sampled pairs in that diagram, numbering the first edge as 1, `z` is high just after edges $2,10,13,15$ and low after every other edge. Equivalently,
$$
\boxed{z_k=1\iff s_k=\mathrm{Pulse},\quad
\mathrm{Pulse}\xrightarrow{b=1}\mathrm{Ready},\quad
\mathrm{Ready}\xrightarrow{a=1,b=0}\mathrm{Pulse}.}
$$
The two low-output states cannot be merged: the same future trigger must produce a pulse from `Ready` and be ignored from `Wait`. A separate high-output state is needed to hold the one-cycle pulse, explaining the three-state design.
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