= Solution
Use $k$ clocked <processor registers>, each storing an $n$-bit word, two independent combinational read ports and one synchronous write port. Each address requires $a=\lceil\log_2k\rceil$ bits. The read addresses select two $k$-to-one <multiplexers>, each $n$ bits wide. A write-address <binary decoder> combines its selected line with the global write enable to form the individual enables:
$$
we_i=\mathrm{RegWrite}\land[\mathrm{wa}=i].
$$
At the active <clock edge>, register $i$ captures the common write data if $we_i=1$, otherwise retaining its word. Reads return the currently stored words selected by their respective addresses. For non-power-of-two $k$, unused address codes need a specified harmless implementation. A simultaneous read and write of one address follows the chosen edge/read timing; an additional forwarding circuit would be needed if a different bypass convention were required.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2017/digital-systems-register-file.png]
{title=Two-read-port register file with a single synchronous write port}
{description=The left panel uses a global write enable; the right shows the MIPS alternative with writes to index zero suppressed. Both read multiplexers select independently, and the alternative returns a hardwired zero for address zero.}
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