= Solution
Connect the fourth <JK flip-flop> with $J_3=K_3=1$ and clock it from $Q_2$, retaining the source's positive-edge convention. Read the four-<bit> state as $Q_3Q_2Q_1Q_0$. Its <state-transition diagram> is a single cycle
$$
0000\to1111\to1110\to\cdots\to0010\to0001\to0000,
$$
with one input rising <clock edge> per arrow; the figure displays every state explicitly.
Each stage halves the preceding triggering <frequency>. \b[$Q_3$ is an ideal <square wave> with a 50-percent <duty cycle> at $1\,\mathrm{GHz}/16=62.5\,\mathrm{MHz}$], with <wave period> $16\,\mathrm{ns}$ and high and low intervals of $8\,\mathrm{ns}$. Its initial phase depends on the starting state. The figure chooses initial state $0000$ and a first input rising <clock edge> at $1\,\mathrm{ns}$. Actual ripple propagation shifts edge times and creates intermediate transient codes; no device delays were supplied, so the waveform describes settled ideal logic.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2021/digital-systems-linear-algebra-introduction-to-formal-proof-ripple-counter.png]
{title=Complete descending four-bit counter cycle and ideal fourth-stage waveform}
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