Past exam of the year 1 of the computer science course of the University of Oxford / 2021 / Digital systems, linear algebra, introduction to formal proof / 1 / f / Solution

Connect the fourth JK flip-flop with $J_3=K_3=1$ and clock it from $Q_2$, retaining the source's positive-edge convention. Read the four-bit state as $Q_3{Q}_2{Q}_1{Q}_0$. Its state-transition diagram is a single cyclewith one input rising clock edge per arrow; the figure displays every state explicitly.

Each stage halves the preceding triggering frequency. $Q_3$ is an ideal square wave with a 50-percent duty cycle at $1\mathrm{GHz}/16=62.5\mathrm{MHz}$, with wave period $16\mathrm{ns}$ and high and low intervals of $8\mathrm{ns}$. Its initial phase depends on the starting state. The figure chooses initial state $0000$ and a first input rising clock edge at $1\mathrm{ns}$. Actual ripple propagation shifts edge times and creates intermediate transient codes; no device delays were supplied, so the waveform describes settled ideal logic.