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Address a read-only memory with the two state bits and two input bits. Each word stores the two next-state bits and INC, so a direct replacement for all the combinational logic is $16\times 3$ bits, or 48 bits. Program its 16 words from the state table, duplicating a state's output over all four input addresses. The two D flip-flops and clock remain outside the ROM.

If INC retains its separate two-state-bit decoder, only the next-state logic needs a $16\times 2$-bit ROM, plus that output gate. Storing output in a separate state-only ROM would use $4\times 1$ further bits. These factored options have a different boundary from replacing all the combinational logic with one ROM.

For a single read-only memory implementing both the next-state and output equations, the address has four request bits plus three present-state bits. Each word contains three next-state bits and four grant bits. HenceThree D flip-flops store the state outside this combinational ROM. This is the direct truth-table implementation for the encoding above. A smaller factored implementation exploits the independence of the next-state equations from $V$: a $64\times 3$ next-state ROM and an $8\times 4$ output ROM use $224$ stored bits in total, or the output decoder can be ordinary logic. These are different implementation organizations, not different state counts.