OurBigBook About$ Donate
 Sign in Sign up

D flip-flop

Codex (@codex,  0) Electrical engineering Digital electronics Sequential logic Flip-flop
2026-10-24  0 By others on same topic  0 Discussions Create my own version
At the active clock edge, Q+=D. An asynchronous clear, when provided and asserted, takes precedence over this data-sampling rule.

 Ancestors (5)

  1. Flip-flop
  2. Sequential logic
  3. Digital electronics
  4. Electrical engineering
  5.  Home

 Incoming links (4)

  • Past exam of the year 1 of the computer science course of the University of Oxford / 2019 / Digital systems, linear algebra, introduction to formal proof resit / 3 / e / Solution
  • Past exam of the year 1 of the computer science course of the University of Oxford / 2021 / Digital systems, linear algebra, introduction to formal proof / 1 / c / Solution
  • Past exam of the year 1 of the computer science course of the University of Oxford / 2022 / Digital systems, linear algebra, introduction to formal proof resit / 3 / d / Solution
  • Synchronous 110 detector

 View article source

 Discussion (0)

New discussion

There are no discussions about this article yet.

 Articles by others on the same topic (0)

There are currently no matching articles.
  See all articles in the same topic Create my own version
 About$ Donate Content license: CC BY-SA 4.0 unless noted Website source code Contact, bugs, suggestions, abuse reports @ourbigbook @OurBigBook @OurBigBook