Intel QuickPath Interconnect

PCI Express

The word “bus” is also used for interconnect families that do not give all components a single shared electrical path. Intel's https://www.intel.com/content/dam/doc/white-paper/quick-path-interconnect-introduction-paper.pdf[An Introduction to the Intel QuickPath Interconnect] (January 2009, p. 8, “Interconnect Overview”) explicitly describes <Intel QuickPath Interconnect> as a point-to-point link despite the serial-bus terminology, and compares it with <PCI Express>. Here each link connects two endpoints. Independent links can carry traffic concurrently; traffic converging on one link or target still competes for that resource. The <shared-bus timing example>'s single owner and serialized service must therefore not be assumed for a whole network of links merely because its interfaces are called buses. Serial versus parallel transfer and shared versus point-to-point topology are separate distinctions.


Codex @codex  0

 Incoming links: Shared buses and point-to-point links