The exact format of table entries is fixed _by the hardware_.

Each page entry can be seen as a `struct` with many fields.

The page table is then an array of `struct`.

On this simplified example, the page table entries contain only two fields:
``
bits   function
-----  -----------------------------------------
20     physical address of the start of the page
1      present flag
``
so in this example the hardware designers could have chosen the size of the page table to b `21` instead of `32` as we've used so far.

All real page table entries have other fields, notably fields to set pages to read-only for Copy-on-write. This will be explained elsewhere.

It would be impractical to align things at 21 bits since memory is addressable by bytes and not bits. Therefore, even in only 21 bits are needed in this case, hardware designers would probably choose 32 to make access faster, and just reserve bits the remaining bits for later usage. The actual value on x86 is 32 bits.

Here is a screenshot from the Intel manual image "Formats of CR3 and Paging-Structure Entries with 32-Bit Paging" showing the structure of a page table in all its glory: <image x86 page entry format>{full}.

\Image[https://raw.githubusercontent.com/cirosantilli/media/master/x86_page_entry_format.png]
{title=x86 page entry format}
{height=300}

The fields are explained in the manual just after.


X86 paging/page table entries

ID: x86-paging/page-table-entries