Lattice Microbes Updated 2025-07-16
GPU accelerated, simulates the Craig's minimized M. genitalium, JCVI-syn3A at a particle basis of some kind.
Lab head is the cutest-looking lady ever: chemistry.illinois.edu/zan, Zaida (Zan) Luthey-Schulten.
- 2022 paper: www.cell.com/cell/fulltext/S0092-8674(21)01488-4 Fundamental behaviors emerge from simulations of a living minimal cell by Thornburg et al. (2022) published on Cell
- faculty.scs.illinois.edu/schulten/lm/ actual source code. No Version control and non-code drop release, openess and best practices haven't reached such far obscure reaches of academia yet. One day.
- blogs.nvidia.com/blog/2022/01/20/living-cell-simulation/ Nvidia announcement. That's how they do business, it is quite interesting how they highlight this kind of research.
List of systems programmers Updated 2025-07-16
Spy Updated 2025-07-16
x86 Paging Tutorial Invalidating TLB entries Updated 2025-07-16
When the process changes,
cr3 change to point to the page table of the new current process.A simple and naive solution would be to completely invalidate the TLB whenever the
cr3 changes.However, this is would not be very efficient, because it often happens that we switch back to process 1 before process 2 has completely used up the entire TLB cache entries.
The solution for this is to use so called "Address Space Identifiers" (ASID) as mentioned in sources such as:
Basically, the OS assigns a different ASID for each process, and then TLB entries are automatically also tagged with that ASID. This way when the process makes an access, the TLB can determine if a hit is actually for the current process, or if it is an old address coincidence with another process.
x86 Paging Tutorial K-ary trees to the rescue Updated 2025-07-16
The algorithmically minded will have noticed that paging requires associative array (like Java
Map of Python dict()) abstract data structure where:The single level paging scheme uses a simple array implementation of the associative array:and in C pseudo-code it looks like this:
- the keys are the array index
- this implementation is very fast in time
- but it is too inefficient in memory
linear_address[0] = physical_address_0
linear_address[1] = physical_address_1
linear_address[2] = physical_address_2
...
linear_address[2^20-1] = physical_address_NBut there another simple associative array implementation that overcomes the memory problem: an (unbalanced) k-ary tree.
Using a K-ary tree instead of an array implementation has the following trade-offs:
In C-pseudo code, a 2-level K-ary tree with and we have the following arrays:
K = 2^10 looks like this:level0[0] = &level1_0[0]
level1_0[0] = physical_address_0_0
level1_0[1] = physical_address_0_1
...
level1_0[2^10-1] = physical_address_0_N
level0[1] = &level1_1[0]
level1_1[0] = physical_address_1_0
level1_1[1] = physical_address_1_1
...
level1_1[2^10-1] = physical_address_1_N
...
level0[N] = &level1_N[0]
level1_N[0] = physical_address_N_0
level1_N[1] = physical_address_N_1
...
level1_N[2^10-1] = physical_address_N_Nand it still contains
2^10 * 2^10 = 2^20 possible keys.K-ary trees can save up a lot of space, because if we only have one key, then we only need the following arrays:
x86 Paging Tutorial Kernel vs process memory layout Updated 2025-07-16
The Linux Kernel reserves two zones of virtual memory:
- one for kernel memory
- one for programs
The exact split is configured by
CONFIG_VMSPLIT_.... By default:- on 32-bit:
- on 64-bit: currently only 48-bits are actually used, split into two equally sized disjoint spaces. The Linux kernel just assigns:
- the bottom part to processes
00000000 00000000to008FFFFF FFFFFFFF - the top part to the kernel:
FFFF8000 00000000toFFFFFFFF FFFFFFFF, like this:------------------ FFFFFFFF Kernel ------------------ C0000000 (not addressable) ------------------ BFFFFFFF Process ------------------ 00000000
- the bottom part to processes
Kernel memory is also paged.
In previous versions, the paging was continuous, but with HIGHMEM this changed.
There is no clear physical memory split: stackoverflow.com/questions/30471742/physical-memory-userspace-kernel-split-on-linux-x86-64
x86 Paging Tutorial Memory management unit Updated 2025-07-16
Paging is done by the Memory Management Unit (MMU) part of the CPU.
It was later integrated into the CPU, but the term MMU still used.
NLab Updated 2025-07-16
Decent encyclopedia of mathematics. Not much motivation, mostly statements though.
Created by:
Nobel Prize Updated 2025-07-16
Web of Stories contains amazing interviews with many (mostly American) winners.
See Surely You're Joking, Mr. Feynman chapter Alfred Nobel's Other Mistake's amazing comments about the Nobel Prize.
TODO who is the digital switch person he mentions?
- www.quora.com/unanswered/Who-was-Richard-Feynman-referring-to-in-the-book-Surely-Youre-Joking-Mr-Feynman-chapter-Alfred-Nobels-Other-Mistake-when-he-talks-about-A-friend-of-mine-whos-a-rich-man-he-invented-some-kind-of-simple-digital-switch on Quora
- github.com/cirosantilli/cirosantilli.github.io/issues/72
Transmon Updated 2025-07-16
Used e.g. in the Sycamore processor.
The most basic type of transmon is in Ciro's ASCII art circuit diagram notation, an LC circuit e.g. as mentioned at youtu.be/cb_f9KpYipk?t=180 from Video "The transmon qubit by Leo Di Carlo (2018)":
+----------+
| Island 1 |
+----------+
| |
X C
| |
+----------+
| Island 2 |
+----------+youtu.be/eZJjQGu85Ps?t=2443 from Video "Superconducting Qubits I Part 1 by Zlatko Minev (2020)" describes a (possibly simplified) physical model of it, as two superconducting metal islands linked up by a Josephson junction marked as The circuit is then analogous to a LC circuit, with the islands being the capacitor. The Josephson junction functions as a non-linear inductor.
X in the diagram as per-Ciro's ASCII art circuit diagram notation:+-------+ +-------+
| | | |
| Q_1() |---X---| Q_2() |
| | | |
+-------+ +-------+Others define it with a SQUID device instead: youtu.be/cb_f9KpYipk?t=328 from Video "The transmon qubit by Leo Di Carlo (2018)". He mentions that this allows tuning the inductive element without creating a new device.
Calibration of Transmon Superconducting Qubits by Stefan Titus (2021)
Source. Possibly this Keysight which would make sense. Trillium Notes Updated 2025-07-16
Originally at github.com/zadam/trilium, then after development stopped the community took it up at: github.com/TriliumNext/Notes.
Tree based organization at last. Infinitely deep.
Amazing WYSIWYG, including maths and tables, plus insane plugins like canvas mode, and specific file formats like code/mermaid diagrams/drawing mode.
Intentionally or not, they've basically made an open source Notion, with the possible exception that Notion historically started on web and moved to the desktop, while Trillium went the other way round.
Version history with automatic snapshots at intervals. TODO how is it implemented? Do they just ZIP multiple versions?
No multiuser features. Except for that, could have been a good starting point of an online multiuser thing such as OurBigBook.com!
With Book Notes it is possible possible to see more than one page at a time on the output, which his a major feature of OurBigBook. But does it show on HTML export as well?
You can static HTML export any subtree by right clicking on it in the navigation tree.
HTML export keeps all data as HTML is their native format. This may be inherited from CKEditor. The files are mostly visible, but there is some CSS missing, it is not 100% like editor, notably math is broken. There is also a hosted way of exposing: github.com/zadam/trilium/wiki/Sharing.
trilium.rocks however has a very good export, it is just a question of how much they had to hacked things, source at: github.com/zerebos/trilium.rocks
The default tHTML export uses frame navigation, with a toc fixed on the left frame. Efficient, but not of this century.
There is no concept of user created unique text IDs: you can have the same headers in the same folders in the UI. It's not even a matter of scopes. On exports they are differentiated as
1_name, 2_name, etc../Trilium Demo/Books/To read/1_HR.md
./Trilium Demo/Books/To read/2_HR.md
./Trilium Demo/Books/To read/HR.mdMarkdown export warns:
this preserves most of the formatting
Architecture: runs on local SQLite database via better-sqlite3. Data apparently stored in SQLite database at
~/.local/share/trilium-data, no raw files.Markup is stored as HTML as seen from:
sqlite3 document.db 'SELECT * from note_contents'. HTML is their native storage format, quite interesting. But this means it is not source centric, so any source editing would have to go via import/export. It can be done apparently: github.com/zadam/trilium/wiki/Markdown but involves shoving a ZIP around.WYSIWYG based on ckeditor.com/ which is a dependency. It is kind of cool that the view in which you view the output is exactly the same as the one you edit in, and there is no intermediate format, just the HTML.
Math is KaTeX based.
It also runs on the browser via a server: github.com/zadam/trilium/wiki/Server-installation. And they have a paid service for it at: trilium.cc/. Quite impressive.
They have server to from desktop sync: github.com/zadam/trilium/wiki/synchronization. There is no conflict resolution, one of them wins randomly. But they have revision history, and anything lost will be in the revision history. They have so many features it is mind blowing.
Maintainer announced he would be slowing down development since January 2024: github.com/zadam/trilium/issues/4620?ref=selfh.st
x86 Paging Tutorial Multi-level paging scheme numerical translation example Updated 2025-07-16
Page directory given to process by the OS:
entry index entry address page table address present
----------- ---------------- ------------------ --------
0 CR3 + 0 * 4 0x10000 1
1 CR3 + 1 * 4 0
2 CR3 + 2 * 4 0x80000 1
3 CR3 + 3 * 4 0
...
2^10-1 CR3 + 2^10-1 * 4 0Page tables given to process by the OS at
PT1 = 0x10000000 (0x10000 * 4K):entry index entry address page address present
----------- ---------------- ------------ -------
0 PT1 + 0 * 4 0x00001 1
1 PT1 + 1 * 4 0
2 PT1 + 2 * 4 0x0000D 1
... ...
2^10-1 PT1 + 2^10-1 * 4 0x00005 1Page tables given to process by the OS at where
PT2 = 0x80000000 (0x80000 * 4K):entry index entry address page address present
----------- --------------- ------------ ------------
0 PT2 + 0 * 4 0x0000A 1
1 PT2 + 1 * 4 0x0000C 1
2 PT2 + 2 * 4 0
...
2^10-1 PT2 + 0x3FF * 4 0x00003 1PT1 and PT2: initial position of page table 1 and page table 2 for process 1 on RAM.With that setup, the following translations would happen:
linear 10 10 12 split physical
-------- -------------- ----------
00000001 000 000 001 00001001
00001001 000 001 001 page fault
003FF001 000 3FF 001 00005001
00400000 001 000 000 page fault
00800001 002 000 001 0000A001
00801004 002 001 004 0000C004
00802004 002 002 004 page fault
00B00001 003 000 000 page faultLet's translate the linear address
0x00801004 step by step:- In binary the linear address is:
0 0 8 0 1 0 0 4 0000 0000 1000 0000 0001 0000 0000 0100 - Grouping as
10 | 10 | 12gives:which gives:0000000010 0000000001 000000000100 0x2 0x1 0x4So the hardware looks for entry 2 of the page directory.page directory entry = 0x2 page table entry = 0x1 offset = 0x4 - The page directory table says that the page table is located at
0x80000 * 4K = 0x80000000. This is the first RAM access of the process. - Finally, the paging hardware adds the offset, and the final address is
0x0000C004.
The Intel manual gives a picture of this translation process in the image "Linear-Address Translation to a 4-KByte Page using 32-Bit Paging": Figure 1. "x86 page translation process"
x86 page translation process
. x86 Paging Tutorial PAE and PSE page table schemes Updated 2025-07-16
If either PAE and PSE are active, different paging level schemes are used:
- no PAE and no PSE:
10 | 10 | 12 - no PAE and PSE:
10 | 22.22 is the offset within the 4Mb page, since 22 bits address 4Mb. - PAE and no PSE:
2 | 9 | 9 | 12The design reason why 9 is used twice instead of 10 is that now entries cannot fit anymore into 32 bits, which were all filled up by 20 address bits and 12 meaningful or reserved flag bits.The reason is that 20 bits are not enough anymore to represent the address of page tables: 24 bits are now needed because of the 4 extra wires added to the processor.Therefore, the designers decided to increase entry size to 64 bits, and to make them fit into a single page table it is necessary reduce the number of entries to 2^9 instead of 2^10. - PAE and PSE:
2 | 9 | 21
Node.js Updated 2025-07-16
WellSync, if you are gonna useSync this wonky language thing inSync one place, you might as well useSync it everywhereSync and make it more decent. See also: how to convert
async to sync in JavaScript.Their CLI debugger is a bit crap compared to GDB, basic functionality is either lacking or too verbose:Documentation at: nodejs.org/dist/latest-v16.x/docs/api/debugger.html
- stackoverflow.com/questions/65493221/how-to-break-at-a-specific-function-or-line-with-the-node-js-node-inspect-comman
- stackoverflow.com/questions/70486188/how-to-break-on-uncaught-exception-on-the-node-js-node-inspect-command-line-debu Some operations are only possible on the browser debug UI...
PyZX Updated 2025-07-16
tshark Updated 2025-07-16
1965 Nobel Prize in Physics laureate Updated 2025-07-16
Closed source is less bad on online services Updated 2025-07-16
Ciro Santilli can accept closed source on server products more easily than offline, because the servers have to be paid for somehow (by stealing your private data).
Euler-Mascheroni constant Updated 2025-07-16
Impenetrable Bose Gas Updated 2025-07-16
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