1. Introduction

The relentless progress in integrated circuit density, governed for decades by the principles of Moore’s Law, has shifted the bottleneck of system design from transistor speed to interconnection complexity. As System-on-Chip (SoC) and massively parallel architectures incorporate billions of transistors, the ability to accurately predict and manage the wiring demands, power consumption, and physical area of a design has become paramount $^5$. Early-stage architectural exploration and physical synthesis rely heavily on robust models that quantify the relationship between logic complexity and communication requirements.

The foundational model in this domain is Rent's Rule $^1$. Discovered empirically by E. F. Rent at IBM in the 1960s, and later formalized by Landman and Russo $^2$, the rule establishes a fundamental power-law relationship between the number of external signal connections (terminals) to a logic block and the number of internal components (gates or standard cells) it contains. Mathematically, the rule is expressed as:

$$T = K \cdot g^{p}$$

Where: $T$ is the number of external terminals (pins/connections); $g$ is the number of internal logic components (gates/blocks); $K$ is the Rent's constant; and $p$ is the Rent exponent.

While Rent's Rule has served as an indispensable tool for wire length estimation $^3, ^4$, placement optimization, and technology prediction, its empirical origins and inherent limitations—especially when applied to modern, highly heterogeneous architectures—necessitate a generalized framework. This paper introduces the New Rule (Tetelbaum's Law), which addresses its primary shortcomings by incorporating explicit structural constraints, thereby extending its utility to the next generation of complex computing systems.

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2. Overview of Rent's Rule and Current Drawbacks
2.1. Current Results and Applications

Rent's Rule describes a statistical self-similarity in the organization of complex digital systems, implying that a circuit partitioned at any level of the hierarchy exhibits the same power-law relationship between pins and gates.

The Rent exponent, $p$, is the central characteristic of the rule and provides immediate insight into a design's topological complexity: $p \approx 0$ corresponds to highly-regular structures; $p \approx 0.5$ is typical of structured designs with high locality (e.g., memory); and $p \approx 0.75$ is characteristic of "random logic" or complex, unstructured designs.

The rule’s primary utility lies in its application to interconnect prediction:
1.	Wire Length Estimation: Donath and others demonstrated that the Rent exponent is directly correlated with the average wire length and distribution $^3$. A lower $p$ value implies greater locality and shorter expected wire lengths, which is crucial for power and timing analysis.

2.	A Priori System Planning: By estimating the Rent exponent early in the design flow, architects can predict necessary routing resources, estimate power dissipation due to interconnects, and evaluate the feasibility of a physical partition before detailed placement and routing $^5$.

2.2. Drawbacks and Limitations

Despite its foundational role, the power-law form of Rent's Rule suffers from several well-documented drawbacks that limit its accuracy and domain of applicability in advanced systems $^6, ^8$:

1.	Terminal Constraint Deviation (Region II): The most significant limitation is the breakdown of the power law for partitions encompassing a very large number of components (i.e., when approaching the size of the entire chip). Since a physical chip has a finite number of peripheral I/O pins, the actual terminal count for the largest partition is physically constrained and ceases to follow the predicted power-law trend. This phenomenon is known as Rent's Region II, where the log-log plot flattens $^7$. This deviation is critical for packaging and system-level planning.

2.	Small Partition Deviation (Region III): A deviation also occurs for very small partitions. This Rent's Region III, often attributed to local wiring effects and the intrinsic definition of the base logic cell, suggests the power-law assumption is inaccurate at the lowest hierarchical levels $^7$.

3.	Assumption of Homogeneity: The theoretical underpinnings of Rent's Rule often assume a statistically homogeneous circuit topology and placement. Modern System-on-Chip (SoC) designs are fundamentally heterogeneous, consisting of diverse functional blocks (e.g., CPU cores, memory controllers, accelerators). Each sub-block exhibits a distinct intrinsic Rent exponent, rendering a single, global Rent parameter insufficient for accurate modeling $^8$.

4.	Inaccuracy for Non-Traditional Architectures: As an empirical model based on traditional VLSI, Rent's Rule is less applicable to highly specialized or non-traditional structures, such as advanced 3D integrated circuits (3D-ICs) or neuromorphic systems, where the physical communication graph significantly deviates from planar assumptions.

These limitations demonstrate a pressing need for a generalized Rent's Rule framework capable of modeling non-uniform locality, structural hierarchy, and physical I/O constraints.

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3. The New Rule: Generalization for Autonomic Systems

Dr. Alexander Tetelbaum utilized a graph-mathematical model to generalize Rent’s Rule, specifically addressing its limitations when applied to autonomic systems. His work demonstrated that the classical power-law form of Rent’s Rule is valid only under the restrictive conditions where the system contains a large number of blocks (designs), and the number $g$ of internal components in a block is much smaller than the total number of components ($N$) in the entire system $^9$.

The generalized formulation, referred to as the New Rule (or Tetelbaum's Law), extends the applicability of the scaling law across the entire range of partition sizes, including the problematic Rent's Region II. The New Rule is expressed as $^9, ^{10}, ^{11}$:

$$T = t \cdot \left( \frac{g \cdot (N - g)}{N - 1} \right)^{P}$$

Where: $T$ is the number of external terminals for the block partition; $N$ is the total number of components in the system; $g$ is the number of components in the block partition; $t$ represents the average number of pins of a component in the system; and $P$ is the generalized Rent exponent, derived by the described graph-partitioning method.

Key Behavioral Cases

The following boundary conditions illustrate the behavior of the New Rule, confirming its consistency with physical constraints and highlighting the overestimation inherent in the classical formulation:

•	Case 1: Single Component ($g = 1$). When a block contains a single component, the New Rule simplifies to $T = t$, which is identical to the behavior of Rent’s Rule.

•	Case 2: Maximum Partition ($g = N/2$). When the system is divided exactly in half, the New Rule yields the maximum terminal count. By contrast, the classical Rent’s Rule, $T = K \cdot g^{p}$, continues to increase as $g$ increases, leading to significant overestimation for large $g$.

•	Case 3: Full System ($g = N$). When the block contains all system components, $N-g=0$, resulting in $T = 0$. This accurately reflects the physical reality that the entire system (if autonomic) has no external signal terminals, thereby explicitly modeling the crucial Rent's Region II terminal constraint deviation $^7$.

Advantages of the New Rule

The New Rule provides several key advantages that address the limitations of the classical power law:

•	Full-Range Analysis: It permits the accurate analysis of system blocks containing an arbitrary number of components.

•	Improved Accuracy: Comparisons between theoretical predictions and empirical data from 28 complex electronic systems demonstrated that terminal count estimations using the New Rule are approximately $\mathbf{4.7\%}$ more accurate than those obtained with Rent’s Rule.

•	Physical Derivation: The constants $t$ and $P$ can be derived directly from the properties of actual designs and systems.

•	Interconnection Estimation: The New Rule enables the accurate estimation of interconnection length distribution for design optimization.

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4. Conclusion

The complexity of modern electronic systems necessitates robust, predictive models for interconnect planning and resource allocation. Rent's Rule has served as a cornerstone for this task, offering a simple yet powerful power-law framework for relating logic complexity to communication demand. However, the rule's inherent empirical limitations—specifically the breakdown at system-level constraints (Region II) and its inaccuracy for heterogeneous architectures—render it increasingly insufficient for the challenges of advanced VLSI and system design.

The proposed New Rule (Tetelbaum's Law) $^9$ represents a critical generalization that resolves these long-standing issues. By explicitly incorporating the total number of system components ($N$) into the formulation, the New Rule accurately models the terminal count across the entire spectrum of partition sizes. Its mathematical form naturally constrains the terminal count to zero when the partition equals the system size ($g=N$), perfectly capturing the physical I/O constraints that define Rent's Region II. Furthermore, the proven $\mathbf{4.7\%}$ accuracy improvement over the classical model confirms its superior predictive capability.

This generalized framework allows architects to perform more reliable, full-system interconnect planning a priori. Future work will focus on extending the New Rule to explicitly model non-uniform locality within heterogeneous SoCs, and applying it to non-traditional geometries, such as 3D integrated circuits, where the concept of locality must be defined across multiple physical layers.

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5.	References

1.	Rent, E.F. (1960): Original discovery (often an internal IBM memorandum).

2.	Landman, L.A. and Russo, R.L. (1971): "On Pin Versus Block Relationship for Partitions of Logic Graphs," IEEE Transactions on Computers, vol. C-20, no. 12, pp. 1469-1479.

3.	Donath, W.E. (1981): "Wire Length Distribution for Computer Logic," IBM Technical Disclosure Bulletin, vol. 23, no. 11, pp. 5865-5868.

4.	Heller, W.R., Hsi, C. and Mikhail, W.F. (1978): "Chip-Level Physical Design: An Overview," IEEE Transactions on Electron Devices, vol. 25, no. 2, pp. 163-176.

5.	Bakoglu, H.B. (1990): Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley.

6.	Sutherland, I.E. and Oosterhout, W.J. (2001): "The Futures of Design: Interconnections," ACM/IEEE Design Automation Conference (DAC), pp. 15-20.

7.	Davis, J. A. and Meindl, J. D. (2000): "A Hierarchical Interconnect Model for Deep Submicron Integrated Circuits," IEEE Transactions on Electron Devices, vol. 47, no. 11, pp. 2068-2073.

8.	Stroobandt, D. A. and Van Campenhout, J. (2000): "The Geometry of VLSI Interconnect," Proceedings of the IEEE, vol. 88, no. 4, pp. 535-546.

9.	TETELBAUM, A. (1995). "Generalizations of Rent's Rule", in Proc. of 27th IEEE Southeastern Symposium on System Theory, Starkville, Mississippi, USA, March 1995, pp. 011-016.

10.	TETELBAUM, A. (1995). "Estimations of Layout Parameters of Hierarchical Systems", in Proc. of 27th IEEE Southeastern Symposium on System Theory, Starkville, Mississippi, USA, March 1995, pp. 123-128.

11.	TETELBAUM, A. (1995). "Estimation of the Graph Partitioning for a Hierarchical System", in Proc. of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, San Francisco, California, USA, February 1995, pp. 500-502.


Natalie Heroux @nheroux 1