 Solution

ID: past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2017/digital-systems-linear-algebra-introduction-to-formal-proof/2/d/solution

With the given ready-order rule and A first, the CPU timeline in milliseconds is

interval CPU 0 : 4 A 4 : 5 B 5 : 6 idle 6 : 10 A 10 : 11 B 11 : 12 idle 12 : 16 A 16 : 17 B

A performs input-output during

[4, 6)

and

[10, 12)

; B does so during

[5, 7)

and

[11, 13)

. In particular, B becoming ready at time 7 does not interrupt A's ongoing nonpreemptive burst. The completion times are

C_{A} = 16

and

C_{B} = 17

elapsed time = 17 ms, mean turnaround = 16.5 ms .

There are 15 ms of useful CPU execution and 2 ms of idle time on this particular timeline.

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