 Solution

Use the stipulated MIPS I-type instruction encoding, whose unused $rt$ field is zero, so register-file output $r{d}_1$ supplies the hardwired zero register. With $\mathrm{ALUSrc}=0$ and subtraction selected, the arithmetic logic unit computes $R[rs]-0$. Its zero flag detects $R[rs]=0$, while bit 31 of $r{d}_0$ is the sign in two's complement. Therefore the required signed test isIntroduce one new control bit $GT$, and replace the zero-flag input to the existing branch XOR byThis needs an AND gate, an OR gate and a tap of the sign bit. With $GT=0$, existing branch behavior is unchanged. With $GT=1$ and $\mathrm{Branch}=11$, the existing branch-taken circuit gives $\neg Z^{\ast }$, exactly the positive test. Its output still selects between $pc+4$ and the usual sign-extended branch target. The complete control row isSet $GT=0$ for each instruction in parts (a)–(c). Registers and data memory remain unchanged. The available signed slt operation could support a different design; the sign-and-zero design above avoids adding an ALU-input swap and explicitly distinguishes zero from positive values.