Solution

ID: past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2021/digital-systems-linear-algebra-introduction-to-formal-proof/1/a/solution

After asserting and releasing the active-low Start pulse, a valid sequence is , then , then , with each input held high through the relevant sampling interval. The first JK flip-flop has and is clocked by , so the rising clock edge of samples and sets . Once that output has settled, a rising clock edge of clocks the second JK flip-flop with , setting .
The essential conditions concern sampled levels: must be high at a rising clock edge of , and must then be high at a rising clock edge of . Separate edges with adequate setup and hold time avoid an ambiguous simultaneous transition.

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