 Solution

Store two bits: the output $z$, initially zero, and an armed bit $e$, initially one. Define the synchronous sequential circuit byHere $\oplus$ is exclusive or, and the input restriction $c\wedge d=0$ excludes conflicting commands. The output is the current stored $z$.

When armed, a sampled $c=1$ toggles $z$ and clears $e$. Further $c$ samples leave the output unchanged. A sampled $d=1$ sets $e=1$ without changing $z$, allowing a later $c$ to toggle it again. The same clock edge cannot both rearm and trigger because $c,d$ are never simultaneously high. Thus the first $c$ toggles from zero to one, and subsequent toggles each require a new $d$ followed by a later $c$.