Synchronous sequential circuit ($s^{\prime }=F(s,a),w=G(s,a)$)

A synchronous sequential circuit stores a finite collection of bits $s$, reads inputs $a$, and updates all stored bits at each clock edge according to a specified next-state function $F$. A combinational output is $G(s,a)$; an output that is itself stored is included among the state bits. An initial state is part of a complete design. These equations provide a precise implementation-level description of a finite-state machine without requiring a particular gate drawing.

A synchronous sequential circuit emitting a one-cycle pulse at the first low sample after at least two consecutive high samples. Three D flip-flops can implement $q_1^{+}=a$, $q_2^{+}=q_1\wedge a$, and $z^{+}=q_2\wedge \neg a$, with all updates using the old state. Initializing all state bits to zero excludes a false startup history. The stored output changes only at clock edges. After a detecting low sample, $q_2$ becomes zero, so the next output is zero regardless of the next input. A longer high run still ends with the same three-sample pattern.

A digital counter is a finite-state circuit that increments its stored value on each qualifying clock or event. A binary $w$-bit implementation naturally has modulus $2^w$. Dividing counted ticks by a known clock frequency gives a time interval, subject to wrap ambiguity and sampling accuracy.

A hardware timer uses a clock signal to measure intervals, commonly by a digital counter with capture or comparison facilities. A comparison event can request an interrupt or change an output directly. Counter resolution, wraparound, interrupt latency and the hardware's comparison semantics determine the timing guarantees available to software.

The displayed two-register Moore machine, initialized to $q_1{q}_0=00$, generates a one-clock pulse on a sampled high when ready, then waits for two consecutive sampled zeros before it can generate another. The codes $00,10,11,01$ represent ready, pulse, disabled and one-zero-seen respectively. From ready a high enters pulse; from pulse the next edge leaves for disabled on a high or one-zero-seen on a low. Disabled enters one-zero-seen on a low. A second consecutive low returns to ready, whereas a high returns to disabled. This transition analysis proves the output rule, the one-period duration and the immediate first-edge response after reset. It assumes a synchronous input meeting setup and hold requirements.