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A group of related payload transfers, often to consecutive addresses, arranged under one transfer sequence. A bus burst can amortize setup and bus arbitration overhead; a longer period of exclusive bus ownership can also make another initiator wait longer. The exact overhead and permitted handover boundaries depend on the protocol.^[ref]

An extension while a bus transaction awaits readiness. A bus wait state spends time without completing the next payload transfer. In a blocking design it also postpones another initiator's access; completion and bus ownership changes must follow the protocol.^[ref]

A computer bus connects components through agreed communication paths and transfer rules. On a shared computer bus, a CPU and a DMA engine can both want the same path to computer memory: attaching another initiator does not create another independent path. Bus arbitration chooses who may start; bus ownership states who may use each resource; bus throughput measures the useful data delivered. This makes sharing a performance question as well as a correctness question.