Cache hierarchy

Several levels of memory cache, typically combining a small low-latency first level with larger later levels. Each level reduces traffic reaching the next; local and global cache miss rates must be distinguished.

Fetching a cache line before a demand access requires it, to overlap transfer latency with useful work. A software prefetch is one way to request this; unnecessary requests can cause cache pollution.

A program-directed hint to fetch a cache line early. A useful nonblocking hint produces no destination processor register value and allows execution to continue before the transfer completes. Fault and dropping behavior depend on the specified instruction contract.