Processor register

A small storage location within a CPU used by its instructions. Some hold data; others describe control state, such as the program counter or stack pointer. Saving and restoring processor registers lets different software threads reuse the same CPU while retaining separate execution contexts.

State bits recording properties of an instruction's result for later conditional operations. A branch must use the flags established by the intended preceding instruction: an intervening flag-setting operation can change its meaning.

A processor condition flag set when the relevant result is zero. A loop that decrements its remaining count and immediately branches on nonzero uses this flag as its termination test. A preceding logical shift's zero result is a different condition.

A processor status bit recording arithmetic carry. For unsigned addition of $n$-bit inputs, $X+Y=Z+2^{n}C$, where $Z$ is the stored result. In the ARM architecture family, subtraction instead uses $X-Y=Z-2^n(1-C)$, so a set arithmetic carry means no borrow. This convention must be checked for the target instruction set; it is not a signed-overflow test.

With the ARM architecture family's no-borrow convention, subtract with carry forms $X-Y-(1-C_{\mathrm{in}})$. The same adder used for addition can form $X+(2^n-1-Y)+C_{\mathrm{in}}$. If its output is $Z+2^n{C}_{\mathrm{out}}$, rearranging proves $X-Y-(1-C_{\mathrm{in}})=Z-2^n(1-C_{\mathrm{out}})$. Thus complementing the second operand implements both the result and the correctly chained borrow information.^[ref]

For $n$-bit operands, an add with carry operation forms $X+Y+C_{\mathrm{in}}$, retains its residue modulo $2^n$, and outputs its arithmetic carry. Adding low limbs first and feeding each arithmetic carry into the next limb implements multiword unsigned addition. With $M=2^n$, the identities $X_0+Y_0=Z_0+Mc$ and $X_1+Y_1+c=Z_1+Md$ combine into $(M{X}_1+X_0)+(M{Y}_1+Y_0)=M{Z}_1+Z_0+M^{2}d$.^[ref]

A collection of indexed processor registers. Selecting one of $R$ registers requires at least $\lceil {\log }_{2}R\rceil$ bits in a register index field.

A destination code whose writes have no architectural effect. Replacing a disabled write by a write to such a destination can remove a global register-file enable input: every actual register enable becomes its address-decode line, and the suppression code activates none. The instruction control must still select that code whenever a write should be suppressed. This transformation preserves the register-state update, rather than making the control decision unnecessary.

Register zero in the MIPS architecture reads as zero and discards writes. An implementation can omit its data storage, hardwire its read output to zero and suppress its write selection. This property permits using zero as a write-suppression destination without changing the visible register values.

Moving a live value from a processor register to memory so the register can be reused, then loading it again when needed.

A processor register identifying the current position in a stack, commonly a call stack; the exact convention depends on the architecture. Restoring a stack pointer selects the saved stack position, rather than copying the whole call stack.