Past exam of the mathematics course of the University of Cambridge / 2006 / ia / Paper 5 / 8 / a / iv / Solution

Separate buses match different bandwidth, latency and electrical requirements. Processor-memory traffic needs high bandwidth and short delays, whereas many peripheral devices are slower or use different signaling protocols. Bridges let them communicate without making every memory transfer obey the slowest peripheral's timing. Separating traffic also reduces contention and electrical loading, and permits expansion or compatibility with older device interfaces. Thus a hierarchical computer bus organization is useful even though all devices are ultimately reachable from the processor.