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A PCI Express root complex connects a host's CPU and memory system to a PCI Express hierarchy. A PCI Express root port originates a downstream link from that complex; one root complex can expose several such ports. Endpoints may attach directly or through switches.^[ref]

For example, an operating system discovers a device through the hierarchy and configures resources through which the host and device communicate. Device-initiated memory transfers also depend on the platform's address mappings and protection mechanisms. The root complex is the host-facing architectural component, while a switch distributes links within the hierarchy and a PCI Express lane is one unit of a link's physical signaling. Keeping those levels separate prevents confusing a port count with a CPU count or a guaranteed bandwidth.

A PCI Express root port is a port in a root complex that starts a PCI Express link leading toward downstream devices or a switch. The PCI Express root port is represented as a logical bridge in the hierarchy. It is distinct from the PCI Express endpoint that provides a device function.^[ref]

For example, a storage PCI Express endpoint can attach directly to one PCI Express root port, while another root port connects to a switch serving several devices. Port services such as error reporting, hot plugging or power management concern that hierarchy and its links. Requiring a root-port service driver is therefore a different task from writing the device driver for the storage endpoint.

A PCI Express switch routes transactions between PCI Express links in a hierarchy. In a conventional single-root arrangement, an upstream port connects toward the root complex and downstream ports connect toward endpoints or further switches. Software sees logical bridge relationships that describe this structure.^[ref]

For example, two devices can have separate downstream links while sharing one upstream link to the host. Their local links can operate independently, but simultaneous host-bound transfers compete for the upstream capacity. Adding ports does not manufacture unlimited host bandwidth. A PCI Express switch routes the interconnect's transactions; its role and addressing model differ from those of an Ethernet switch.

Tom L Nguyen is the author credited on the Linux kernel's guide to the PCI Express port bus driver, with an Intel email address in its byline. The guide explains how a single port can provide several services, including hot-plug handling and error reporting, while the ordinary driver model associates one driver with a device.^[ref]

The port bus driver coordinates those services so separate service drivers can coexist instead of competing to claim the same bridge. This is a concrete example of dividing operating-system kernel responsibilities around one physical device. The cited document establishes the technical authorship; it does not justify expanding the name's initials or assigning a biography to a namesake.