Three-sample run detector ($w_t=a_t\wedge a_{t-1}\wedge a_{t-2}$)

Store the two previous input bits in $p,q$. At the next clock edge, use $w=a\wedge p\wedge q$ and update $(p,q{)}^{\prime }=(a,p)$. The output is high exactly when the present input and previous two samples are all high. Replacing each input by its negation detects a three-sample low run. Both detectors can share the same two history bits, using $a\wedge p\wedge q$ and $\neg a\wedge \neg p\wedge \neg q$. With initial history zero, the high detector cannot trigger before three actual high samples have occurred.