Gate timing jitter is shot-to-shot variation in the timing of a detection time gate relative to the signal being measured. It differs from a fixed delay error: repeated gates may have the correct mean delay while admitting different portions of a rapidly varying detector signal. The SR250 catalogue describes a trigger-controlled gate, finite delay jitter and a gate-monitor output that can be overlaid with the signal on an oscilloscope.[ref]
For an original sensitivity derivation, let a reproducible baseline-corrected electric current waveform be and the intended integrated electric charge beSmall edge errors giveIf both edges shift by the same amount, the gate width is unchanged butThus a gate translating within a flat plateau has little first-order sensitivity, while a gate whose edges intersect different signal levels can be sensitive even at fixed width.
For stipulated edge currents and , a common timing error with standard deviation contributes approximately charge standard deviation. This calculation assumes smooth waveform values near both edges and timing excursions small enough for linearization. A gate crossing an abrupt onset requires the actual waveform integral.
Gate-width jitter is a separate effect. For a constant plateau current , , so even though a common gate translation would cancel. More generally, the edge-error contribution has varianceThe covariance determines whether two individually noisy edges largely preserve the width.
An apparatus check records both the gate monitor and signal waveform over many triggers, using the same time reference, to estimate relative delay and width distributions. A single aligned trace establishes neither distribution. Timing motion shared by the pulse and gate can cancel in their relative delay; the uncertainty relevant to the measured charge is their relative timing, not solely a gate generator's standalone specification.
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